![intel 3.1 extensible host controller asus intel 3.1 extensible host controller asus](https://s3.manualzz.com/store/data/055183997_1-f4d90e2c0776e1f8c3081506bd396029.png)
![intel 3.1 extensible host controller asus intel 3.1 extensible host controller asus](https://imagizer.imageshack.us/v2/1280x1024q90/28/fbis.jpg)
The partial and slumber states save interface power when the interface is idle. Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller specification defines these states as sub-states of the device D0 state. The link PM exit latency from this state to active state maximum is 20 ms, unless otherwise specified by DETO in Identify Device Data Log page 08h (Refer to SATA Rev3.2 Gold specification). The link PM exit latency to active state maximum is 10 ms. Slumber – PHY logic is powered up, and in a reduced power state.The link PM exit latency to active state maximum is 10 ns. Partial – PHY logic is powered up, and in a reduced power state.PHY READY – PHY logic and PLL are both on and in active state.However, an ACPI method is also called which will reset the device and then cut its power.Įach of these device states are subsets of the host controller’s D0 state.įinally, the SATA specification defines three PHY layer power states, which have no equivalent mappings to parallel ATA. D3 – From the SATA device’s perspective, no different than a D1 state, in that it is entered using the STANDBY IMMEDIATE command.Exit latency from this state is in seconds. D1 – Device enters when it receives a STANDBY IMMEDIATE command.D0 – Device is working and instantly available.The three device states are supported through ACPI. SATA adopted 3 main power states from parallel ATA. SATA devices may also have multiple power states. The D0 PCI Power Management (PM) state for device is supported by the PCH SATA controller. Power management of the PCH SATA controller and ports will cover operations of the host controller and the SATA link.